The present invention relates to a microprocessor and, more particularly, to a microprocessor operable in a functional redundancy monitor (called hereinafter "FRM") mode for supporting a multiple processor system.
As a microprocessor is progressed in performance and function, the application thereof extends to high reliability systems such as an electronic exchanger, an on-line terminal in a bank system, a medical apparatus, etc. For a high reliability system, a multiple processor structure is employed, which includes a microprocessor operating in a normal mode and another microprocessor operating in an FRM mode, these microprocessors being interconnected through address, data and control buses along with a system memory and various peripheral units to structure the multiple processor system.
The normal mode microprocessor operates as a control processing unit of the system. Namely, it drives the buses to output an address, fetches an instruction via the bus, executes the fetched instruction, and drives the buses to read or write operand data. On the other hand, the FRM mode microprocessor operates in synchronism with the normal mode microprocessor, but does not drive the buses. Namely, the FRM mode microprocessor simultaneously fetches the same instruction and operand data as those fetched by the normal mode microprocessor and executes the instruction. The FRM mode microprocessor also generates internally addresses for fetching the instruction and for reading and writing operand data and operand data to be written, but does not drive the buses by use of the internally generated addresses and operand data. Then, the FRM mode microprocessor compares the addresses and data generated by itself with those generated and outputted onto the buses by the normal mode microprocessor, and outputs to the external the comparison resultant as a match signal. This match signal takes one logic level when the addresses and data generated by the FRM mode microprocessor are coincident with those generated by the normal mode microprocessor to thereby inform that the normal mode microprocessor operates normally, but takes the other logic level when both of them are not coincident with each other to thereby inform that the normal mode microprocessor does not operate normally.
The FRM mode microprocessor carries out the above-mentioned comparison operation every time a bus cycle is started. The logic level of the match signal representative of the comparison resultant in a current bus cycle is held until a next bus cycle is started to obtain the comparison resultant in that cycle. For this reason, if the normal mode microprocessor operates abnormally during the idling period between the adjacent bus cycles or the period of the microprocessor having to be in the operation halt or stop state, the FRM mode microprocessor does not change the match signal to the logic level representative of the maloperation of the normal mode microprocessor during that period. The acknowledgement of the maloperation of the normal mode microprocessor is thereby delayed.